Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/KrsticC97
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/et/KrsticC97
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Angela_Krstic
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Kwang-Ting_Cheng
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1023%2FA%3A1008295716980
>
foaf:
homepage
<
https://doi.org/10.1023/A:1008295716980
>
dc:
identifier
DBLP journals/et/KrsticC97
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1023%2FA%3A1008295716980
(xsd:string)
dcterms:
issued
1997
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/et
>
rdfs:
label
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Angela_Krstic
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Kwang-Ting_Cheng
>
swrc:
number
1
(xsd:string)
swrc:
pages
43-54
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/et/KrsticC97/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/et/KrsticC97
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/et/et11.html#KrsticC97
>
rdfs:
seeAlso
<
https://doi.org/10.1023/A:1008295716980
>
dc:
subject
VLSI testing; delay testing; resynthesis for testability; path delay faults; timing defects
(xsd:string)
dc:
title
Resynthesis of Combinational Circuits for Path Count Reduction and for Path Delay Fault Testability.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
11
(xsd:string)