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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/et/LiLWLWNMC15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Haibin_Wang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Li_Chen_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Lixiang_Li_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michael_Newton>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qiong_Wu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rui_Liu_0011>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuan_Ma>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yuanqing_Li>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs10836-015-5549-x>
foaf:homepage <https://doi.org/10.1007/s10836-015-5549-x>
dc:identifier DBLP journals/et/LiLWLWNMC15 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs10836-015-5549-x (xsd:string)
dcterms:issued 2015 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/et>
rdfs:label Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Haibin_Wang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Li_Chen_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Lixiang_Li_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michael_Newton>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qiong_Wu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rui_Liu_0011>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuan_Ma>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yuanqing_Li>
swrc:number 5-6 (xsd:string)
swrc:pages 561-568 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/et/LiLWLWNMC15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/et/LiLWLWNMC15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/et/et31.html#LiLWLWNMC15>
rdfs:seeAlso <https://doi.org/10.1007/s10836-015-5549-x>
dc:title Simulation and Experimental Evaluation of a Soft Error Tolerant Layout for SRAM 6T Bitcell in 65nm Technology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 31 (xsd:string)