Test program synthesis for modules and chips having boundary scan.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/LienB93
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dcterms:
bibliographicCitation
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http://dblp.uni-trier.de/rec/bibtex/journals/et/LienB93
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dc:
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https://dblp.l3s.de/d2r/resource/authors/Jung-Cheun_Lien
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dc:
creator
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https://dblp.l3s.de/d2r/resource/authors/Melvin_A._Breuer
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homepage
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http://dx.doi.org/doi.org%2F10.1007%2FBF00971645
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DBLP journals/et/LienB93
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issued
1993
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Test program synthesis for modules and chips having boundary scan.
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https://dblp.l3s.de/d2r/resource/authors/Jung-Cheun_Lien
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https://dblp.l3s.de/d2r/resource/authors/Melvin_A._Breuer
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swrc:
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2
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pages
159-180
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dc:
subject
Board and system test; boundary scan; built-in self-test; design-for-test; test controllers; test program synthesis
(xsd:string)
dc:
title
Test program synthesis for modules and chips having boundary scan.
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4
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