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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/et/MiuraNF97>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiromu_Fujioka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Katsuyoshi_Miura>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Koji_Nakamae>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1023%2FA%3A1008271709747>
foaf:homepage <https://doi.org/10.1023/A:1008271709747>
dc:identifier DBLP journals/et/MiuraNF97 (xsd:string)
dc:identifier DOI doi.org%2F10.1023%2FA%3A1008271709747 (xsd:string)
dcterms:issued 1997 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/et>
rdfs:label Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiromu_Fujioka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Katsuyoshi_Miura>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Koji_Nakamae>
swrc:number 3 (xsd:string)
swrc:pages 255-269 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/et/MiuraNF97/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/et/MiuraNF97>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/et/et10.html#MiuraNF97>
rdfs:seeAlso <https://doi.org/10.1023/A:1008271709747>
dc:subject hierarchical fault tracing; electron beam testing; hierarchically structured CAD layout; successive circuit extraction (xsd:string)
dc:title Hierarchical VLSI Fault Tracing by Successive Circuit Extraction from CAD Layout Data in the CAD-Linked EB Test System. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 10 (xsd:string)