Trade-offs in scan path and BIST implementations for RAMs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/NicolaidisKA94
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1994
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Trade-offs in scan path and BIST implementations for RAMs.
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273-283
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dc:
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Aliasing; BIST; coupling faults; RAM test algorithms; scan path; signature analysis
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Trade-offs in scan path and BIST implementations for RAMs.
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