A methodology for testability enhancement at layout level.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/TeixeiraTAGG91
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DBLP journals/et/TeixeiraTAGG91
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1991
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A methodology for testability enhancement at layout level.
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4
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287-299
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dc:
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fault modeling; physical design rules for testability; simulation; testability analysis
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A methodology for testability enhancement at layout level.
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