Design Error Diagnosis with Re-Synthesis in Combinational Circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/Ubar03
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dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/et/Ubar03
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dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Raimund_Ubar
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foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1023%2FA%3A1021948013402
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foaf:
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DBLP journals/et/Ubar03
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dc:
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DOI doi.org%2F10.1023%2FA%3A1021948013402
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dcterms:
issued
2003
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swrc:
journal
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https://dblp.l3s.de/d2r/resource/journals/et
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rdfs:
label
Design Error Diagnosis with Re-Synthesis in Combinational Circuits.
(xsd:string)
foaf:
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<
https://dblp.l3s.de/d2r/resource/authors/Raimund_Ubar
>
swrc:
number
1
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swrc:
pages
73-82
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http://bibsonomy.org/uri/bibtexkey/journals/et/Ubar03/dblp
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rdfs:
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http://dblp.uni-trier.de/db/journals/et/et19.html#Ubar03
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rdfs:
seeAlso
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https://doi.org/10.1023/A:1021948013402
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dc:
subject
design error; diagnosis; fault simulation; test generation
(xsd:string)
dc:
title
Design Error Diagnosis with Re-Synthesis in Combinational Circuits.
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type
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swrc:Article
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