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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/et/VenerisCAS05>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Andreas_G._Veneris>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Magdy_S._Abadir>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Robert_Chang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sep_Seyedi>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs10836-005-1543-z>
foaf:homepage <https://doi.org/10.1007/s10836-005-1543-z>
dc:identifier DBLP journals/et/VenerisCAS05 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs10836-005-1543-z (xsd:string)
dcterms:issued 2005 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/et>
rdfs:label Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Andreas_G._Veneris>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Magdy_S._Abadir>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Robert_Chang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sep_Seyedi>
swrc:number 5 (xsd:string)
swrc:pages 495-502 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/et/VenerisCAS05/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/et/VenerisCAS05>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/et/et21.html#VenerisCAS05>
rdfs:seeAlso <https://doi.org/10.1007/s10836-005-1543-z>
dc:subject VLSI; test generation; diagnostic test generation; fault (xsd:string)
dc:title Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 21 (xsd:string)