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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/et/VillaTGVB19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Eduardo_Augusto_Bezerra>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fabian_Luis_Vargas_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Paulo_Ricardo_Cechelero_Villa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rodrigo_Travessini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Roger_C._Goerl>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs10836-019-05778-z>
foaf:homepage <https://doi.org/10.1007/s10836-019-05778-z>
dc:identifier DBLP journals/et/VillaTGVB19 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs10836-019-05778-z (xsd:string)
dcterms:issued 2019 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/et>
rdfs:label Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Eduardo_Augusto_Bezerra>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fabian_Luis_Vargas_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Paulo_Ricardo_Cechelero_Villa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rodrigo_Travessini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Roger_C._Goerl>
swrc:number 1 (xsd:string)
swrc:pages 9-27 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/et/VillaTGVB19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/et/VillaTGVB19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/et/et35.html#VillaTGVB19>
rdfs:seeAlso <https://doi.org/10.1007/s10836-019-05778-z>
dc:title Fault Tolerant Soft-Core Processor Architecture Based on Temporal Redundancy. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 35 (xsd:string)