A neural network algorithm for testing stuck-open faults in CMOS combinational circuits.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/et/ZhangMP93
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1993
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A neural network algorithm for testing stuck-open faults in CMOS combinational circuits.
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Neural networks; stuck-open and gate delay faults; test pattern generation
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A neural network algorithm for testing stuck-open faults in CMOS combinational circuits.
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