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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/et/ZivkovicTK02>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hans_G._Kerkhoff>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ronald_J._W._T._Tangelder>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/V._A._Zivkovic>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1023%2FA%3A1014901829507>
foaf:homepage <https://doi.org/10.1023/A:1014901829507>
dc:identifier DBLP journals/et/ZivkovicTK02 (xsd:string)
dc:identifier DOI doi.org%2F10.1023%2FA%3A1014901829507 (xsd:string)
dcterms:issued 2002 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/et>
rdfs:label An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hans_G._Kerkhoff>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ronald_J._W._T._Tangelder>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/V._A._Zivkovic>
swrc:number 2 (xsd:string)
swrc:pages 203-212 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/et/ZivkovicTK02/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/et/ZivkovicTK02>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/et/et18.html#ZivkovicTK02>
rdfs:seeAlso <https://doi.org/10.1023/A:1014901829507>
dc:subject VLIW processor test; test synthesis; Design for Testability (DfT); test-time analysis (xsd:string)
dc:title An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 18 (xsd:string)