An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits.
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bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/fcsc/HeXGXSHZZRW17
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Fei_Gu_0001
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Li_Ruan
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Limin_Xiao
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Longbing_Zhang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Rong_Zhang
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Shubin_Su
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Tongsheng_Xia
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Xiang_Wang_0006
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zhenxue_He
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zhisheng_Huo
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1007%2Fs11704-016-5259-2
>
foaf:
homepage
<
https://doi.org/10.1007/s11704-016-5259-2
>
dc:
identifier
DBLP journals/fcsc/HeXGXSHZZRW17
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1007%2Fs11704-016-5259-2
(xsd:string)
dcterms:
issued
2017
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/fcsc
>
rdfs:
label
An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Fei_Gu_0001
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Li_Ruan
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Limin_Xiao
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Longbing_Zhang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Rong_Zhang
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Shubin_Su
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Tongsheng_Xia
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Xiang_Wang_0006
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zhenxue_He
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zhisheng_Huo
>
swrc:
number
4
(xsd:string)
swrc:
pages
728-742
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/fcsc/HeXGXSHZZRW17/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/fcsc/HeXGXSHZZRW17
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/fcsc/fcsc11.html#HeXGXSHZZRW17
>
rdfs:
seeAlso
<
https://doi.org/10.1007/s11704-016-5259-2
>
dc:
title
An efficient and fast polarity optimization approach for mixed polarity Reed-Muller logic circuits.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
11
(xsd:string)