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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/fmsd/ChevallierEFX09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Emmanuelle_Encrenaz-Tiph%E2%88%9A%C2%AEne>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Laurent_Fribourg>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Remy_Chevallier>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Weiwen_Xu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1007%2Fs10703-008-0061-x>
foaf:homepage <https://doi.org/10.1007/s10703-008-0061-x>
dc:identifier DBLP journals/fmsd/ChevallierEFX09 (xsd:string)
dc:identifier DOI doi.org%2F10.1007%2Fs10703-008-0061-x (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/fmsd>
rdfs:label Timed verification of the generic architecture of a memory circuit using parametric timed automata. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Emmanuelle_Encrenaz-Tiph%E2%88%9A%C2%AEne>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Laurent_Fribourg>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Remy_Chevallier>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Weiwen_Xu>
swrc:number 1 (xsd:string)
swrc:pages 59-81 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/fmsd/ChevallierEFX09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/fmsd/ChevallierEFX09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/fmsd/fmsd34.html#ChevallierEFX09>
rdfs:seeAlso <https://doi.org/10.1007/s10703-008-0061-x>
dc:subject Memory circuit; Timed automata; Model checking (xsd:string)
dc:title Timed verification of the generic architecture of a memory circuit using parametric timed automata. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 34 (xsd:string)