A Formalization of a Subset of VHDL in the Boyer-Moore Logic. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/David_M._Russinoff>
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dc:identifier	DBLP journals/fmsd/Russinoff95 (xsd:string)
dc:identifier	DOI doi.org%2F10.1007%2FBF01383871 (xsd:string)
dcterms:issued	1995 (xsd:gYear)
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rdfs:label	A Formalization of a Subset of VHDL in the Boyer-Moore Logic. (xsd:string)
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dc:title	A Formalization of a Subset of VHDL in the Boyer-Moore Logic. (xsd:string)
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