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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/hcis/SaravananAW15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Alagan_Anpalagan>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Isaac_Woungang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Vijayalakshmi_Saravanan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1186%2Fs13673-015-0046-x>
foaf:homepage <https://doi.org/10.1186/s13673-015-0046-x>
dc:identifier DBLP journals/hcis/SaravananAW15 (xsd:string)
dc:identifier DOI doi.org%2F10.1186%2Fs13673-015-0046-x (xsd:string)
dcterms:issued 2015 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/hcis>
rdfs:label An energy-delay product study on chip multi-processors for variable stage pipelining. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Alagan_Anpalagan>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Isaac_Woungang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Vijayalakshmi_Saravanan>
swrc:pages 28 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/hcis/SaravananAW15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/hcis/SaravananAW15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/hcis/hcis5.html#SaravananAW15>
rdfs:seeAlso <https://doi.org/10.1186/s13673-015-0046-x>
dc:title An energy-delay product study on chip multi-processors for variable stage pipelining. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 5 (xsd:string)