[RDF data]
Home | Example Publications
PropertyValue
dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieiceee/GeHHLZ20>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bo_Liu_0019>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ji_Quan_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Min_Zhu_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shenxin_Hu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Wei_Ge>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Felex.16.20190670>
foaf:homepage <https://doi.org/10.1587/elex.16.20190670>
dc:identifier DBLP journals/ieiceee/GeHHLZ20 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Felex.16.20190670 (xsd:string)
dcterms:issued 2020 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieiceee>
rdfs:label FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bo_Liu_0019>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ji_Quan_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Min_Zhu_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shenxin_Hu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Wei_Ge>
swrc:number 2 (xsd:string)
swrc:pages 20190670 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieiceee/GeHHLZ20/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieiceee/GeHHLZ20>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee17.html#GeHHLZ20>
rdfs:seeAlso <https://doi.org/10.1587/elex.16.20190670>
dc:title FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 17 (xsd:string)