A highly reliable FPGA-based RO PUF with enhanced challenge response pairs resilient to modeling attacks.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/ieiceee/HeWKZCJ21
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A highly reliable FPGA-based RO PUF with enhanced challenge response pairs resilient to modeling attacks.
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A highly reliable FPGA-based RO PUF with enhanced challenge response pairs resilient to modeling attacks.
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