A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/ieiceee/HwangJS08
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A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface.
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A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface.
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