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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieiceee/JiangHWWM15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jianfei_Jiang_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jizeng_Wei>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Qin_Wang_0009>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Weifeng_He>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhigang_Mao>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Felex.12.20150111>
foaf:homepage <https://doi.org/10.1587/elex.12.20150111>
dc:identifier DBLP journals/ieiceee/JiangHWWM15 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Felex.12.20150111 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieiceee>
rdfs:label Design optimization for capacitive-resistively driven on-chip global interconnect. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jianfei_Jiang_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jizeng_Wei>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Qin_Wang_0009>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Weifeng_He>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhigang_Mao>
swrc:number 8 (xsd:string)
swrc:pages 20150111 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieiceee/JiangHWWM15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieiceee/JiangHWWM15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee12.html#JiangHWWM15>
rdfs:seeAlso <https://doi.org/10.1587/elex.12.20150111>
dc:title Design optimization for capacitive-resistively driven on-chip global interconnect. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 12 (xsd:string)