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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieiceee/JoBMK09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ji-Hye_Bong>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kwan-Hee_Jo>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kyeong-Sik_Min>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sung-Mo_Kang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Felex.6.1414>
foaf:homepage <https://doi.org/10.1587/elex.6.1414>
dc:identifier DBLP journals/ieiceee/JoBMK09 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Felex.6.1414 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieiceee>
rdfs:label A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ji-Hye_Bong>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kwan-Hee_Jo>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kyeong-Sik_Min>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sung-Mo_Kang>
swrc:number 19 (xsd:string)
swrc:pages 1414-1420 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieiceee/JoBMK09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieiceee/JoBMK09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee6.html#JoBMK09>
rdfs:seeAlso <https://doi.org/10.1587/elex.6.1414>
dc:title A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 6 (xsd:string)