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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieiceee/XuWLCY23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Faxin_Yu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hua_Chen>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jiarui_Liu_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yantian_Xu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhiyu_Wang>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Felex.20.20230035>
foaf:homepage <https://doi.org/10.1587/elex.20.20230035>
dc:identifier DBLP journals/ieiceee/XuWLCY23 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Felex.20.20230035 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieiceee>
rdfs:label Multi-chip phase synchronization circuit of fractional-N PLL. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Faxin_Yu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hua_Chen>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jiarui_Liu_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yantian_Xu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhiyu_Wang>
swrc:number 9 (xsd:string)
swrc:pages 20230035 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieiceee/XuWLCY23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieiceee/XuWLCY23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee20.html#XuWLCY23>
rdfs:seeAlso <https://doi.org/10.1587/elex.20.20230035>
dc:title Multi-chip phase synchronization circuit of fractional-N PLL. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 20 (xsd:string)