A resource and timing optimized PCIe DMA architecture using FPGA internal data buffer. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dcterms:bibliographicCitation	<http://dblp.uni-trier.de/rec/bibtex/journals/ieiceee/ZhaoLY19>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jiong_Yang>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Xin_Liu>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Yingxiao_Zhao>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1587%2Felex.15.20180858>
foaf:homepage	<https://doi.org/10.1587/elex.15.20180858>
dc:identifier	DBLP journals/ieiceee/ZhaoLY19 (xsd:string)
dc:identifier	DOI doi.org%2F10.1587%2Felex.15.20180858 (xsd:string)
dcterms:issued	2019 (xsd:gYear)
swrc:journal	<https://dblp.l3s.de/d2r/resource/journals/ieiceee>
rdfs:label	A resource and timing optimized PCIe DMA architecture using FPGA internal data buffer. (xsd:string)
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jiong_Yang>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Xin_Liu>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Yingxiao_Zhao>
swrc:number	1 (xsd:string)
swrc:pages	20180858 (xsd:string)
owl:sameAs	<http://bibsonomy.org/uri/bibtexkey/journals/ieiceee/ZhaoLY19/dblp>
owl:sameAs	<http://dblp.rkbexplorer.com/id/journals/ieiceee/ZhaoLY19>
rdfs:seeAlso	<http://dblp.uni-trier.de/db/journals/ieiceee/ieiceee16.html#ZhaoLY19>
rdfs:seeAlso	<https://doi.org/10.1587/elex.15.20180858>
dc:title	A resource and timing optimized PCIe DMA architecture using FPGA internal data buffer. (xsd:string)
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rdf:type	swrc:Article
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swrc:volume	16 (xsd:string)