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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/HirayamaSYN14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hayato_Sugawara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Katsuhisa_Yamanaka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Takashi_Hirayama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yasuaki_Nishitani>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Ftransinf.2013LOP0013>
foaf:homepage <https://doi.org/10.1587/transinf.2013LOP0013>
dc:identifier DBLP journals/ieicet/HirayamaSYN14 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Ftransinf.2013LOP0013 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieicet>
rdfs:label A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hayato_Sugawara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Katsuhisa_Yamanaka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Takashi_Hirayama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yasuaki_Nishitani>
swrc:number 9 (xsd:string)
swrc:pages 2253-2261 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieicet/HirayamaSYN14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieicet/HirayamaSYN14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieicet/ieicet97d.html#HirayamaSYN14>
rdfs:seeAlso <https://doi.org/10.1587/transinf.2013LOP0013>
dc:title A Lower Bound on the Gate Count of Toffoli-Based Reversible Logic Circuits. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 97-D (xsd:string)