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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/IshiharaTKHK11>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masanori_Hariyama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Michitaka_Kameyama>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ryoto_Tsuchiya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shota_Ishihara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yoshiya_Komatsu>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Ftransele.E94.C.1669>
foaf:homepage <https://doi.org/10.1587/transele.E94.C.1669>
dc:identifier DBLP journals/ieicet/IshiharaTKHK11 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Ftransele.E94.C.1669 (xsd:string)
dcterms:issued 2011 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieicet>
rdfs:label Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masanori_Hariyama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Michitaka_Kameyama>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ryoto_Tsuchiya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shota_Ishihara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yoshiya_Komatsu>
swrc:number 10 (xsd:string)
swrc:pages 1669-1679 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieicet/IshiharaTKHK11/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieicet/IshiharaTKHK11>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieicet/ieicet94c.html#IshiharaTKHK11>
rdfs:seeAlso <https://doi.org/10.1587/transele.E94.C.1669>
dc:title Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 94-C (xsd:string)