A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/ieicet/LiaoAILK13
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2013
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A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine.
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A Design of High Performance Parallel Architecture and Communication for Multi-ASIP Based Image Processing Engine.
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