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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/MasudaH19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masanori_Hashimoto>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yutaka_Masuda>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Ftransfun.E102.A.867>
foaf:homepage <https://doi.org/10.1587/transfun.E102.A.867>
dc:identifier DBLP journals/ieicet/MasudaH19 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Ftransfun.E102.A.867 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieicet>
rdfs:label MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masanori_Hashimoto>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yutaka_Masuda>
swrc:number 7 (xsd:string)
swrc:pages 867-877 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieicet/MasudaH19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieicet/MasudaH19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieicet/ieicet102a.html#MasudaH19>
rdfs:seeAlso <https://doi.org/10.1587/transfun.E102.A.867>
dc:title MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 102-A (xsd:string)