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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/NakasatoOSF07>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hideo_Fujiwara>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kewal_K._Saluja>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masato_Nakasato>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Satoshi_Ohtake>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1093%2Fietisy%2Fe90-1.1.296>
foaf:homepage <https://doi.org/10.1093/ietisy/e90-1.1.296>
dc:identifier DBLP journals/ieicet/NakasatoOSF07 (xsd:string)
dc:identifier DOI doi.org%2F10.1093%2Fietisy%2Fe90-1.1.296 (xsd:string)
dcterms:issued 2007 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieicet>
rdfs:label Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hideo_Fujiwara>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kewal_K._Saluja>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masato_Nakasato>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Satoshi_Ohtake>
swrc:number 1 (xsd:string)
swrc:pages 296-305 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieicet/NakasatoOSF07/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieicet/NakasatoOSF07>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieicet/ieicet90d.html#NakasatoOSF07>
rdfs:seeAlso <https://doi.org/10.1093/ietisy/e90-1.1.296>
dc:title Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 90-D (xsd:string)