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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/OhtomoKNN08>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Koizumi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kazuyoshi_Nishimura>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masafumi_Nogawa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yusuke_Ohtomo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1093%2Fietele%2Fe91-c.4.655>
foaf:homepage <https://doi.org/10.1093/ietele/e91-c.4.655>
dc:identifier DBLP journals/ieicet/OhtomoKNN08 (xsd:string)
dc:identifier DOI doi.org%2F10.1093%2Fietele%2Fe91-c.4.655 (xsd:string)
dcterms:issued 2008 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieicet>
rdfs:label A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-¬Ķm CMOS/SOI. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hiroshi_Koizumi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kazuyoshi_Nishimura>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masafumi_Nogawa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yusuke_Ohtomo>
swrc:number 4 (xsd:string)
swrc:pages 655-661 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieicet/OhtomoKNN08/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieicet/OhtomoKNN08>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieicet/ieicet91c.html#OhtomoKNN08>
rdfs:seeAlso <https://doi.org/10.1093/ietele/e91-c.4.655>
dc:title A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-¬Ķm CMOS/SOI. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 91-C (xsd:string)