A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 ¬Ķm Bipolar-CMOS-DMOS Process.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/ieicet/ParkKSSJJ11
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A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 ¬Ķm Bipolar-CMOS-DMOS Process.
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A Non-snapback ESD Protection Clamp Circuit Using Isolated Parasitic Capacitance in a 0.35 ¬Ķm Bipolar-CMOS-DMOS Process.
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