Modeling and Simulation of Via-Connected Power Bus Stacks in Multilayer PCBs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/ieicet/WangWHYTK05
Home
|
Example Publications
Property
Value
dcterms:
bibliographicCitation
<
http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/WangWHYTK05
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Osami_Wada
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Ryuji_Koga
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Takahiro_Yaguchi
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Takashi_Harada
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Yoshitaka_Toyota
>
dc:
creator
<
https://dblp.l3s.de/d2r/resource/authors/Zhi_Liang_Wang
>
foaf:
homepage
<
http://dx.doi.org/doi.org%2F10.1093%2Fietcom%2Fe88-b.8.3176
>
foaf:
homepage
<
https://doi.org/10.1093/ietcom/e88-b.8.3176
>
dc:
identifier
DBLP journals/ieicet/WangWHYTK05
(xsd:string)
dc:
identifier
DOI doi.org%2F10.1093%2Fietcom%2Fe88-b.8.3176
(xsd:string)
dcterms:
issued
2005
(xsd:gYear)
swrc:
journal
<
https://dblp.l3s.de/d2r/resource/journals/ieicet
>
rdfs:
label
Modeling and Simulation of Via-Connected Power Bus Stacks in Multilayer PCBs.
(xsd:string)
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Osami_Wada
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Ryuji_Koga
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Takahiro_Yaguchi
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Takashi_Harada
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Yoshitaka_Toyota
>
foaf:
maker
<
https://dblp.l3s.de/d2r/resource/authors/Zhi_Liang_Wang
>
swrc:
number
8
(xsd:string)
swrc:
pages
3176-3181
(xsd:string)
owl:
sameAs
<
http://bibsonomy.org/uri/bibtexkey/journals/ieicet/WangWHYTK05/dblp
>
owl:
sameAs
<
http://dblp.rkbexplorer.com/id/journals/ieicet/WangWHYTK05
>
rdfs:
seeAlso
<
http://dblp.uni-trier.de/db/journals/ieicet/ieicet88b.html#WangWHYTK05
>
rdfs:
seeAlso
<
https://doi.org/10.1093/ietcom/e88-b.8.3176
>
dc:
title
Modeling and Simulation of Via-Connected Power Bus Stacks in Multilayer PCBs.
(xsd:string)
dc:
type
<
http://purl.org/dc/dcmitype/Text
>
rdf:
type
swrc:Article
rdf:
type
foaf:Document
swrc:
volume
88-B
(xsd:string)