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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/XuSIO19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hidetoshi_Onodera>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hongjie_Xu>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jun_Shiomi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tohru_Ishihara>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Ftransfun.E102.A.1741>
foaf:homepage <https://doi.org/10.1587/transfun.E102.A.1741>
dc:identifier DBLP journals/ieicet/XuSIO19 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Ftransfun.E102.A.1741 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieicet>
rdfs:label On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hidetoshi_Onodera>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hongjie_Xu>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jun_Shiomi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tohru_Ishihara>
swrc:number 12 (xsd:string)
swrc:pages 1741-1750 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieicet/XuSIO19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieicet/XuSIO19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieicet/ieicet102a.html#XuSIO19>
rdfs:seeAlso <https://doi.org/10.1587/transfun.E102.A.1741>
dc:title On-Chip Cache Architecture Exploiting Hybrid Memory Structures for Near-Threshold Computing. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 102-A (xsd:string)