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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/YamadaJSGS17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Junji_Yamada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Goshima>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ryota_Shioya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shuichi_Sakai>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ushio_Jimbo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Ftransele.E100.C.232>
foaf:homepage <https://doi.org/10.1587/transele.E100.C.232>
dc:identifier DBLP journals/ieicet/YamadaJSGS17 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Ftransele.E100.C.232 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieicet>
rdfs:label Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Junji_Yamada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Masahiro_Goshima>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ryota_Shioya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shuichi_Sakai>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ushio_Jimbo>
swrc:number 3 (xsd:string)
swrc:pages 232-244 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieicet/YamadaJSGS17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieicet/YamadaJSGS17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieicet/ieicet100c.html#YamadaJSGS17>
rdfs:seeAlso <https://doi.org/10.1587/transele.E100.C.232>
dc:title Design of a Register Cache System with an Open Source Process Design Kit for 45nm Technology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 100-C (xsd:string)