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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/YanoNIA17>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Kunihiro_Asada>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tetsuya_Iizuka>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Tomohiko_Yano>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Toru_Nakura>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Ftransele.E100.C.736>
foaf:homepage <https://doi.org/10.1587/transele.E100.C.736>
dc:identifier DBLP journals/ieicet/YanoNIA17 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Ftransele.E100.C.736 (xsd:string)
dcterms:issued 2017 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieicet>
rdfs:label A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Kunihiro_Asada>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tetsuya_Iizuka>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Tomohiko_Yano>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Toru_Nakura>
swrc:number 9 (xsd:string)
swrc:pages 736-745 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieicet/YanoNIA17/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieicet/YanoNIA17>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieicet/ieicet100c.html#YanoNIA17>
rdfs:seeAlso <https://doi.org/10.1587/transele.E100.C.736>
dc:title A Gate Delay Mismatch Tolerant Time-Mode Analog Accumulator Using a Delay Line Ring. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 100-C (xsd:string)