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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ieicet/ZangK09>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chengjie_Zang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Shinji_Kimura>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1587%2Ftransfun.E92.A.1454>
foaf:homepage <https://doi.org/10.1587/transfun.E92.A.1454>
dc:identifier DBLP journals/ieicet/ZangK09 (xsd:string)
dc:identifier DOI doi.org%2F10.1587%2Ftransfun.E92.A.1454 (xsd:string)
dcterms:issued 2009 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ieicet>
rdfs:label Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chengjie_Zang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Shinji_Kimura>
swrc:number 6 (xsd:string)
swrc:pages 1454-1463 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ieicet/ZangK09/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ieicet/ZangK09>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ieicet/ieicet92a.html#ZangK09>
rdfs:seeAlso <https://doi.org/10.1587/transfun.E92.A.1454>
dc:title Finite Input-Memory Automaton Based Checker Synthesis of SystemVerilog Assertions for FPGA Prototyping. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 92-A (xsd:string)