Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/ieicetb/KorikawaKHO21
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2021
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Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM.
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Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM.
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