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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/iet-cdt/BandyopadhyayDC19>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Anupam_Chattopadhyay>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Chandan_Bandyopadhyay>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Hafizur_Rahaman_0001>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rakesh_Das>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1049%2Fiet-cdt.2017.0097>
foaf:homepage <https://doi.org/10.1049/iet-cdt.2017.0097>
dc:identifier DBLP journals/iet-cdt/BandyopadhyayDC19 (xsd:string)
dc:identifier DOI doi.org%2F10.1049%2Fiet-cdt.2017.0097 (xsd:string)
dcterms:issued 2019 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/iet-cdt>
rdfs:label Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Anupam_Chattopadhyay>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Chandan_Bandyopadhyay>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Hafizur_Rahaman_0001>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rakesh_Das>
swrc:number 1 (xsd:string)
swrc:pages 38-48 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/iet-cdt/BandyopadhyayDC19/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/iet-cdt/BandyopadhyayDC19>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/iet-cdt/iet-cdt13.html#BandyopadhyayDC19>
rdfs:seeAlso <https://doi.org/10.1049/iet-cdt.2017.0097>
dc:title Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 13 (xsd:string)