Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/iet-cdt/GuptaC21
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Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA.
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Coupled variable-input LCG and clock divider-based large period pseudo-random bit generator on FPGA.
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