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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/iet-cdt/HuangGSZ21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mangu_Song>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xiaoying_Huang>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Xuewen_Zeng>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Zhichuan_Guo>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1049%2Fcdt2.12034>
foaf:homepage <https://doi.org/10.1049/cdt2.12034>
dc:identifier DBLP journals/iet-cdt/HuangGSZ21 (xsd:string)
dc:identifier DOI doi.org%2F10.1049%2Fcdt2.12034 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/iet-cdt>
rdfs:label Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mangu_Song>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xiaoying_Huang>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Xuewen_Zeng>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Zhichuan_Guo>
swrc:number 6 (xsd:string)
swrc:pages 427-436 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/iet-cdt/HuangGSZ21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/iet-cdt/HuangGSZ21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/iet-cdt/iet-cdt15.html#HuangGSZ21>
rdfs:seeAlso <https://doi.org/10.1049/cdt2.12034>
dc:title Accelerating the SM3 hash algorithm with CPU-FPGA Co-Designed architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 15 (xsd:string)