Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Surajit_Kumar_Roy>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1049%2Fiet-cdt.2014.0137>
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Surajit_Kumar_Roy>
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swrc:pages	268-274 (xsd:string)
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dc:title	Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips. (xsd:string)
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