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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ijahuc/SinghCA23>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Bibhudendra_Acharya>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Pulkit_Singh>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rahul_Kumar_Chaurasiya>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1504%2FIJAHUC.2023.10055684>
foaf:homepage <https://doi.org/10.1504/IJAHUC.2023.10055684>
dc:identifier DBLP journals/ijahuc/SinghCA23 (xsd:string)
dc:identifier DOI doi.org%2F10.1504%2FIJAHUC.2023.10055684 (xsd:string)
dcterms:issued 2023 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ijahuc>
rdfs:label Modelling and optimisation of high-speed KLEIN architectures on FPGA and ASIC platforms for IoT applications. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Bibhudendra_Acharya>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Pulkit_Singh>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rahul_Kumar_Chaurasiya>
swrc:number 4 (xsd:string)
swrc:pages 207-225 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ijahuc/SinghCA23/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ijahuc/SinghCA23>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ijahuc/ijahuc42.html#SinghCA23>
rdfs:seeAlso <https://doi.org/10.1504/IJAHUC.2023.10055684>
dc:title Modelling and optimisation of high-speed KLEIN architectures on FPGA and ASIC platforms for IoT applications. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 42 (xsd:string)