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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ijcaet/NirmalJ21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Uma_Nirmal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/V._K._Jain>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1504%2FIJCAET.2021.114490>
foaf:homepage <https://doi.org/10.1504/IJCAET.2021.114490>
dc:identifier DBLP journals/ijcaet/NirmalJ21 (xsd:string)
dc:identifier DOI doi.org%2F10.1504%2FIJCAET.2021.114490 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ijcaet>
rdfs:label Divide-by-16/17 dual modulus prescaler design with enhanced speed in a 180nm CMOS technology. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Uma_Nirmal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/V._K._Jain>
swrc:number 3 (xsd:string)
swrc:pages 345-357 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ijcaet/NirmalJ21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ijcaet/NirmalJ21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ijcaet/ijcaet14.html#NirmalJ21>
rdfs:seeAlso <https://doi.org/10.1504/IJCAET.2021.114490>
dc:title Divide-by-16/17 dual modulus prescaler design with enhanced speed in a 180nm CMOS technology. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 14 (xsd:string)