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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ijccc/MathanaBH14>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/J._Magdalene_Mathana>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Rani_Hemamalini>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/S._Badrinarayanan>
foaf:homepage <http://dx.doi.org/doi.org%2F10.15837%2Fijccc.2014.2.111>
foaf:homepage <https://doi.org/10.15837/ijccc.2014.2.111>
dc:identifier DBLP journals/ijccc/MathanaBH14 (xsd:string)
dc:identifier DOI doi.org%2F10.15837%2Fijccc.2014.2.111 (xsd:string)
dcterms:issued 2014 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ijccc>
rdfs:label VLSI Architecture for High Performance 3GPP Interleaver/Deinterleaver for Turbo Codes. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/J._Magdalene_Mathana>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Rani_Hemamalini>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/S._Badrinarayanan>
swrc:number 2 (xsd:string)
swrc:pages 187-200 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ijccc/MathanaBH14/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ijccc/MathanaBH14>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ijccc/ijccc9.html#MathanaBH14>
rdfs:seeAlso <https://doi.org/10.15837/ijccc.2014.2.111>
dc:title VLSI Architecture for High Performance 3GPP Interleaver/Deinterleaver for Turbo Codes. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 9 (xsd:string)