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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ijcta/ChalkiadakiVPB13>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9dric_Valla>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_Poullet>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Maria-Anna_Chalkiadaki>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Matthias_Bucher>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1002%2Fcta.1833>
foaf:homepage <https://doi.org/10.1002/cta.1833>
dc:identifier DBLP journals/ijcta/ChalkiadakiVPB13 (xsd:string)
dc:identifier DOI doi.org%2F10.1002%2Fcta.1833 (xsd:string)
dcterms:issued 2013 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ijcta>
rdfs:label Why- and how- to integrate Verilog-A compact models in SPICE simulators. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/C%E2%88%9A%C2%A9dric_Valla>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Fr%E2%88%9A%C2%A9d%E2%88%9A%C2%A9ric_Poullet>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Maria-Anna_Chalkiadaki>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Matthias_Bucher>
swrc:number 11 (xsd:string)
swrc:pages 1203-1211 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ijcta/ChalkiadakiVPB13/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ijcta/ChalkiadakiVPB13>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ijcta/ijcta41.html#ChalkiadakiVPB13>
rdfs:seeAlso <https://doi.org/10.1002/cta.1833>
dc:title Why- and how- to integrate Verilog-A compact models in SPICE simulators. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 41 (xsd:string)