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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ijcta/Domenech-Asensi13>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Gin%E2%88%9A%C2%A9s_Dom%E2%88%9A%C2%A9nech-Asensi>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_%E2%88%9A%C4%80ngel_D%E2%88%9A%E2%89%A0az-Madrid>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ram%E2%88%9A%E2%89%A5n_Ruiz_Merino>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1002%2Fcta.820>
foaf:homepage <https://doi.org/10.1002/cta.820>
dc:identifier DBLP journals/ijcta/Domenech-Asensi13 (xsd:string)
dc:identifier DOI doi.org%2F10.1002%2Fcta.820 (xsd:string)
dcterms:issued 2013 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ijcta>
rdfs:label Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Gin%E2%88%9A%C2%A9s_Dom%E2%88%9A%C2%A9nech-Asensi>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Jos%E2%88%9A%C2%A9_%E2%88%9A%C4%80ngel_D%E2%88%9A%E2%89%A0az-Madrid>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ram%E2%88%9A%E2%89%A5n_Ruiz_Merino>
swrc:number 7 (xsd:string)
swrc:pages 732-742 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ijcta/Domenech-Asensi13/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ijcta/Domenech-Asensi13>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ijcta/ijcta41.html#Domenech-Asensi13>
rdfs:seeAlso <https://doi.org/10.1002/cta.820>
dc:title Synthesis of CMOS analog circuit VHDL-AMS descriptions using parameterizable macromodels. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 41 (xsd:string)