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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ijcta/ManisankarC18>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Sivasundar_Manisankar>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Yeonbae_Chung>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1002%2Fcta.2496>
foaf:homepage <https://doi.org/10.1002/cta.2496>
dc:identifier DBLP journals/ijcta/ManisankarC18 (xsd:string)
dc:identifier DOI doi.org%2F10.1002%2Fcta.2496 (xsd:string)
dcterms:issued 2018 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ijcta>
rdfs:label P-channel logic 2 T eDRAM macro with high retention bit architecture. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Sivasundar_Manisankar>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Yeonbae_Chung>
swrc:number 7 (xsd:string)
swrc:pages 1416-1425 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ijcta/ManisankarC18/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ijcta/ManisankarC18>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ijcta/ijcta46.html#ManisankarC18>
rdfs:seeAlso <https://doi.org/10.1002/cta.2496>
dc:title P-channel logic 2 T eDRAM macro with high retention bit architecture. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 46 (xsd:string)