Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/ijertcs/ZhangZCKVAL11
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Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.
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Optimized Communication Architecture of MPSoCs with a Hardware Scheduler: A System-Level Analysis.
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