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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ijes/MenendezGLL21>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Ariel_Lutenberg>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Facundo_S._Larosa>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Mart%E2%88%9A%E2%89%A0n_N._Men%E2%88%9A%C2%A9ndez>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Santiago_Germino>
foaf:homepage <http://dx.doi.org/doi.org%2F10.1504%2FIJES.2021.121088>
foaf:homepage <https://doi.org/10.1504/IJES.2021.121088>
dc:identifier DBLP journals/ijes/MenendezGLL21 (xsd:string)
dc:identifier DOI doi.org%2F10.1504%2FIJES.2021.121088 (xsd:string)
dcterms:issued 2021 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ijes>
rdfs:label Automatic generation of VHDL code for a railway interlocking system. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Ariel_Lutenberg>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Facundo_S._Larosa>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Mart%E2%88%9A%E2%89%A0n_N._Men%E2%88%9A%C2%A9ndez>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Santiago_Germino>
swrc:number 6 (xsd:string)
swrc:pages 544-552 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ijes/MenendezGLL21/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ijes/MenendezGLL21>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ijes/ijes14.html#MenendezGLL21>
rdfs:seeAlso <https://doi.org/10.1504/IJES.2021.121088>
dc:title Automatic generation of VHDL code for a railway interlocking system. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 14 (xsd:string)