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dcterms:bibliographicCitation <http://dblp.uni-trier.de/rec/bibtex/journals/ijfsa/RahejaDR15>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Reena_Dadhich>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Smita_Rajpal>
dc:creator <https://dblp.l3s.de/d2r/resource/authors/Supriya_Raheja>
foaf:homepage <http://dx.doi.org/doi.org%2F10.4018%2FIJFSA.2015070103>
foaf:homepage <https://doi.org/10.4018/IJFSA.2015070103>
dc:identifier DBLP journals/ijfsa/RahejaDR15 (xsd:string)
dc:identifier DOI doi.org%2F10.4018%2FIJFSA.2015070103 (xsd:string)
dcterms:issued 2015 (xsd:gYear)
swrc:journal <https://dblp.l3s.de/d2r/resource/journals/ijfsa>
rdfs:label Designing of Vague Logic Based Fair-Share CPU Scheduler: VFS CPU Scheduler. (xsd:string)
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Reena_Dadhich>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Smita_Rajpal>
foaf:maker <https://dblp.l3s.de/d2r/resource/authors/Supriya_Raheja>
swrc:number 3 (xsd:string)
swrc:pages 25-49 (xsd:string)
owl:sameAs <http://bibsonomy.org/uri/bibtexkey/journals/ijfsa/RahejaDR15/dblp>
owl:sameAs <http://dblp.rkbexplorer.com/id/journals/ijfsa/RahejaDR15>
rdfs:seeAlso <http://dblp.uni-trier.de/db/journals/ijfsa/ijfsa4.html#RahejaDR15>
rdfs:seeAlso <https://doi.org/10.4018/IJFSA.2015070103>
dc:title Designing of Vague Logic Based Fair-Share CPU Scheduler: VFS CPU Scheduler. (xsd:string)
dc:type <http://purl.org/dc/dcmitype/Text>
rdf:type swrc:Article
rdf:type foaf:Document
swrc:volume 4 (xsd:string)