Designing a graphics processing unit accelerated petaflop capable lattice Boltzmann solver: Read aligned data layouts and asynchronous communication. | D2R Server publishing the DBLP Bibliography Database, hosted at L3S Research Center

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dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Jan_Westerholm>
dc:creator	<https://dblp.l3s.de/d2r/resource/authors/Keijo_Mattila>
foaf:homepage	<http://dx.doi.org/doi.org%2F10.1177%2F1094342016658109>
foaf:homepage	<https://doi.org/10.1177/1094342016658109>
dc:identifier	DBLP journals/ijhpca/RobertsenWM17 (xsd:string)
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dcterms:issued	2017 (xsd:gYear)
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rdfs:label	Designing a graphics processing unit accelerated petaflop capable lattice Boltzmann solver: Read aligned data layouts and asynchronous communication. (xsd:string)
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foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Jan_Westerholm>
foaf:maker	<https://dblp.l3s.de/d2r/resource/authors/Keijo_Mattila>
swrc:number	3 (xsd:string)
swrc:pages	246-255 (xsd:string)
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dc:title	Designing a graphics processing unit accelerated petaflop capable lattice Boltzmann solver: Read aligned data layouts and asynchronous communication. (xsd:string)
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