Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs.
Resource URI: https://dblp.l3s.de/d2r/resource/publications/journals/ijhpsa/KhurshidM16
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Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs.
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Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs.
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